1. Field of the Invention
The present invention relates to a driver circuit of a semiconductor device and a semiconductor device using the driver circuit. Particularly, the invention relates to a driver circuit of a semiconductor display device for displaying a picture on a pixel portion by driving TFTs arranged in a matrix form. Further, the invention relates to a semiconductor display device using the driver circuit, particularly to a liquid crystal display device and an EL display device which is also called a light emitting device or a light emitting diode or an OLED (Organic Light Emission Diode). The EL (electroluminescent) devices referred to in this specification include triplet-based light emission devices and-or singlet-based light emission devices, for example.
2. Description of the Related Art
Recently, a technique for fabricating a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, for example, a thin film transistor (TFT), has been rapidly developing.
Among thin film transistors, especially a polycrystalline silicon thin film (poly-Si TFT) can operate at high speed as compared with an amorphous thin film transistor. On this account, different from the case where the amorphous thin film transistor is used, in a semiconductor device using the polycrystalline silicon thin film transistor, a driver circuit can be directly formed on the same substrate as a pixel portion. Note that, in the present specification, an insulating substrate having a surface on which a semiconductor element is formed is called an active matrix substrate.
At present, the mainstream is a system (dot sequential analog system) in which as a video signal itself to be inputted to a driver circuit, an analog signal formed by an IC externally attached to a panel is written in a pixel as it is.
However, as an interface is digitized after this, it is presumed that a system (digital system) in which a video signal of a digital form, which is not decoded into an analog value, is directly taken into a driver circuit on a substrate, and the video signal of the digital form is converted into a video signal of an analog form by the driver circuit, will be more earnestly demanded.
FIG. 24 is a schematic view showing an example of an active matrix liquid crystal display device driven by a dot sequential analog system.
A source side driver circuit 1301 and a gate side driver circuit 1302 are parts of a driver circuit. In a pixel portion 1308, source signal lines 1303 connected to the source side driver circuit 1301 intersect with gate signal lines 1304 connected to the gate side driver circuit 1302. A pixel thin film transistor (pixel TFT) 1305, a liquid crystal cell 1306 in which a liquid crystal is sandwiched between a counter electrode and a pixel electrode, and a storage capacitor 1307 are provided in a region including the source signal line 1303 and the gate signal line 1304.
An analog video signal (analog signal containing image information) inputted to the source signal line 1303 is selected by the pixel TFT 1305 and is written in a predetermined pixel electrode.
The analog video signal sampled by a timing signal outputted from the source side driver circuit 1301 is supplied to the source signal line 1303.
The pixel TFT 1305 is operated by a selection signal inputted from the gate side driver circuit 1302 through the gate signal line 1304.
FIG. 25 is a schematic view showing a structure of an active matrix liquid crystal display device of a digital driver system. In this case, an active matrix liquid crystal display device of a 4-bit digital driver system is exemplified. The active matrix liquid crystal display device of the digital driver system includes, as shown in FIG. 25, a source side driver circuit 1412, a gate side driver circuit 1409, and a pixel portion 1413.
The source side driver circuit 1412 includes a shift register 1401, latches 1 (LAT 1) 1403, latches 2 (LAT 2) 1404, and D/A converter circuits 1406. Address lines 1402(a-d) of digital video signals (digital signals including image information) inputted from the outside are connected to the latches 1 (LAT 1) 1403. A latch pulse line 1405 is connected to the latches 2 (LAT 2) 1404. A gray-scale voltage line 1407 is connected to the D/A converter circuits 1406. Each of the latches 1 1403 and the latches 2 1404 (LAT 1 and LAT 2) represents four latches in one bundle for convenience.
Source signal lines (also called data lines) 1408 connected to the D/A converter circuits 1406 of the source side driver circuit 1412 and gate signal lines (also called scanning lines) 1410 connected to the gate side driver circuit 1409 are provided in the pixel portion 1413.
In the pixel portion 1413, a pixel TFT 1411 and a liquid crystal cell 1414 are provided at a portion where the source signal line 1408 intersects with the gate signal line 1410.
By the timing signal from the shift register 1401, digital video signals supplied to the address lines 1402(a-d) are sequentially written in all the latches 1 1403. Note that, in this specification, all the latches 1 1403 are generally named a LAT 1 group.
A period in which writing of digital video signals into the LAT 1 group is once completed is called one line period. That is, one line period is a period from a point of time when writing of the digital video signal into the leftmost LAT 1 starts to a point of time when writing of the digital video signal into the rightmost LAT 1 is completed. Note that a combination of the period when writing of the digital video signals into the LAT 1 group is once completed and a horizontal retrace line period may be made one line period.
After the writing of the digital video signals into the LAT 1 group is completed, the digital video signals written in the LAT 1 group are transmitted and written into all the latches 2 1404 all at once by a latch signal inputted to the latch pulse line 1405. Note that, in the present specification, all the latches 2 are generically named a LAT 2 group.
After the digital video signals are transmitted to the LAT 2 group, a second line period starts. Thus, by a timing signal from the shift register 1401, writing of digital video signals supplied to the address lines 1402(a-d) is sequentially performed again to the LAT 1 group.
At the same time as the start of this second one line period, the digital video signals written in the LAT 2 group are inputted to the D/A converter circuits 1406 all at once. The inputted digital video signals are converted into analog signals (analog gray-scale voltage signals) having voltages corresponding to image information of the digital video signals by the D/A converter circuits 1406, and are supplied to the source signal lines 1408.
The analog gray-scale voltage signals are supplied to the corresponding source signal lines 1408 during the one line period. Switching of the corresponding pixel TFT 1411 is performed by a selection signal outputted from the gate side driver circuit 1409, and a liquid crystal molecule is driven by the analog gray-scale voltage signal from the source signal line 1408.
The foregoing operation is repeated a predetermined number of times, the number being equal to the number of the gate signal lines, so that one screen (one frame) is formed. In general, in the active matrix liquid crystal display device, rewriting of images of 60 frames is performed in one second.
As described above, in the dot sequential analog system, a gray-scale display corresponding to a voltage of the analog video signal made of one analog gray-scale signal is effected. On the other hand, in the case of the digital driver system, in order to effect a display of, for example, 16 gray-scales, it is necessary to process a 4-bit digital video signal in the driver circuit. To this end, in the digital driver system, compared with the dot sequential analog system in which one analog signal is processed, it becomes necessary to provide a predetermined number of circuits for processing the digital video signal in the driver circuit, the number of the circuits being equal to the number of bits of the digital video signal. For example, in the case of the active matrix liquid crystal display device of the digital driver system corresponding to the 4-bit digital video signal, it becomes necessary to provide four latches for the latch 1 (LAT 1) and four latches for the latch 2 (LAT 2).
Besides, in order to increase the number of gray-scales of an image to be displayed, it is necessary to increase the number of bits of a digital video signal inputted to the driver circuit. If the number of bits of the digital video signal is increased, the number of circuits for processing the digital video signal in the driver circuit is also increased, and the driver circuit becomes massive and complicated. Thus, compared with the dot sequential analog system, in the digital driver system, the number of TFTs included in the driver circuit is drastically increased.
In the dot sequential analog system, it has been easy to operate the source side driver circuit in synchronization with a single clock signal. However, in the digital driver system, compared with the dot sequential analog system, the driver circuit becomes massive and complicated, and the number of TFTs included in the driver circuit is drastically increased. Thus, the resistance of wiring lines or the like, and the capacitor (gate capacitor) formed between gate electrodes of TFTs and active layers become large as compared with the case of the dot sequential analog system. Thus, even if a single clock signal is inputted to the driver circuit, a delay of the clock signal occurs in the driver circuit, and the plurality of circuits in the same driver circuit operate in synchronization with clock signals respectively having different phases. Thus, there occurs a case where transmission of signals among the plurality of circuits is not satisfactorily performed, and there is increased a fear that driving of the driver circuit by the single clock signal becomes difficult.
Thus, in the active matrix liquid crystal display device of the digital driver system, the delay of the clock signal has been prevented to such a degree that driving of the driver circuit does not become difficult, by dividing the same clock signal into a plurality of parts and inputting them to the driver circuit, or by providing a buffer circuit in a wiring line to which the clock signal is inputted.
However, strictly speaking, even if a single clock signal is divided into a plurality of parts and they are inputted to the driver circuit, before the clock signals of the plurality of divided parts are respectively inputted to a plurality of objective circuits, the signals are delayed by wiring capacitor, and the phase shift is produced in the respective clock signals. Besides, if the gate capacitors of TFTs constituting the plurality of circuits in the driver circuit are different among the respective circuits, the clock signal is delayed when it is inputted to the respective circuits, and a shift in the phase is generated.
Even in the case where the buffer circuit is provided in the wiring line to which the clock signal is inputted, the delay of a clock signal inputted to the respective circuits in the driver circuit is caused by the wiring capacitor and the gate capacitor of the TFT constituting the buffer circuit, and phase shift is generated in the clock signal.
In recent years, as the number of pixels is increased to achieve high definition of a semiconductor display device including the active matrix liquid crystal display device, it becomes necessary to drive the source side driver circuit at a higher frequency. For that purpose, it also becomes necessary to increase the frequency of a clock signal inputted to the source side driver circuit.
When the frequency of the clock signal becomes high, the ratio of phase shift to one period becomes large. If the ratio of phase shift to one period among the clock signals inputted to the respective circuits becomes large, transmission of data among the circuits is not performed, or even if transmission is performed, the phase of the digital data after the transmission is shifted since a period for reading the data is short.
In view of the above, an object of the present invention is to perform transmission of data of a digital form without fail in two circuits respectively operating in synchronization with two clock signals having the same frequencies, in which even if phase shift is generated between the two clock signals, there does not occur such a case that data transmission is not performed or the phase of the data is shifted after the transmission.
The present inventor has presumed that in a driver circuit for driving by a single clock signal, clock signals inputted to a plurality of circuits included in the driver circuit mutually include shifts in the phases, that is, the plurality of circuits respectively operate in synchronization with clock signals the phases of which are shifted from each other.
The magnitude of the phase shift (in the present specification, called phase difference) between clock signals inputted to the respective circuits is random and is from a minus half period to a plus half period. Then, for the purpose of transmitting data (digital data) of a digital form from a circuit A synchronizing with a clock signal CK1 (first clock signal) to a circuit B synchronizing with another clock signal CK2 (second clock signal), the present inventor provides a transmission circuit between the circuit A and the circuit B, which recognizes a phase difference between the clock signals CK1 and CK2 and adjusts the timing of transmission of the digital data between the circuits in accordance with the phase difference.
Note that, in the present specification, the digital data means signals of all digital forms relating to driving of a semiconductor device. Thus, a digital video signal is included in the digital data.
With the above structure, in the two circuits respectively synchronizing with the two clock signals having the same frequency, transmission of digital data can be correctly performed irrespective of the phase difference of the clock signals. Specifically, there does not occur such a case that transmission of the digital data is not performed or even if transmission is performed, the phase of the digital data after the transmission is shifted, since a period for reading the digital data is short.
The structure of a transmission circuit according to the present invention will be set forth below.
According to the present invention, there is provided a transmission circuit for transmitting digital data from a first circuit operating in synchronization with a first clock signal to a second circuit operating in synchronization with a second clock signal having the same frequency as the first clock signal, wherein the transmission circuit is characterized in that
in a case where a phase of the second clock signal is delayed from a phase of the first clock signal by not less than zero and not larger than half a period, the digital data inputted from the first circuit to the transmission circuit and synchronizing with the first clock signal is converted into digital data synchronizing with the second clock signal and is outputted from the transmission circuit, and the digital data outputted from the transmission circuit is sampled and held in synchronization with the second clock signal by the second circuit, and
in a case where the phase of the second clock signal leads the phase of the first clock signal by not less zero and not larger than half the period, the digital data inputted from the first circuit to the transmission circuit and synchronizing with the first clock signal is outputted from the transmission circuit as it is or after it is inverted, and the digital data outputted from the transmission circuit is sampled and held in synchronization with the second clock signal by the second circuit.
Besides, according to the present invention, there is provided a transmission circuit for transmitting digital data from a first circuit operating in synchronization with a first clock signal to a second circuit operating in synchronization with a second clock signal having the same frequency as the first clock signal, wherein the transmission circuit is characterized in that
the first clock signal and the second clock signal are inputted to the transmission circuit,
in a case where a phase of the second clock signal is delayed from a phase of the first clock signal by not less than zero and not larger than half a period, the digital data inputted from the first circuit to the transmission circuit and synchronizing with the first clock signal is converted into digital data synchronizing with the second clock signal and is outputted from the transmission circuit, and the digital data outputted from the transmission circuit is sampled and held in synchronization with the second clock signal by the second circuit, and
in a case where the phase of the second clock signal leads the phase of the first clock signal by not less zero and not larger than half the period, the digital data inputted from the first circuit to the transmission circuit and synchronizing with the first clock signal is outputted from the transmission circuit as it is or after it is inverted, and the digital data outputted from the transmission circuit is sampled and held in synchronization with the second clock signal by the second circuit.
Besides, according to the present invention, there is provided a transmission circuit for transmitting digital data from a first circuit operating in synchronization with a first clock signal to a second circuit operating in synchronization with a second clock signal having the same frequency as the first clock signal, wherein the transmission circuit is characterized in that
the transmission circuit includes a plurality of logical circuits,
the transmission circuit selects, according to a phase difference between the first clock signal and the second clock signal, whether the digital data inputted to the transmission circuit is outputted as it is or after it is reversed, or the digital data inputted to the transmission circuit is sampled in synchronization with the second clock signal and is outputted as it is or after it is inverted, and the digital data outputted from the transmission circuit is sampled and held in synchronization with the second clock signal by the second c ircuit.
The logical circuit includes a clocked inverter, an inverter, a NOR, a NAND, an OR, an AND, and an analog switch.
In the second circuit, the length of a period in which one bit of the digital data outputted from the transmission circuit is sampled may be the same as the length of half the period of the first clock signal or the second clock signal.
A semiconductor device is characterized by including the transmission circuit.
The semiconductor device may be a liquid crystal display device.
The semiconductor device may be an EL display device.